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jsenesi's avatar
jsenesi
Icon for New Contributor rankNew Contributor
5 years ago
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1G/10G PHY single reference clock

I have been asked to implement the 1G/10Gbe PHY design on Arria 10 based hardware that only provides a 644.53125 MHz reference oscillator. Our typical implementations include the 125 MHz reference for 1Gbe.

I have been able to build the design with two cascaded fPLLs producing the 125 and 625MHz references required for the 1GbE operational mode.

10GbE works just fine. 1Gbe mode does not work. When I try to switch to 1GbE the calibration sequence never completes; signal 'rc_busy' remains active..

I am monitoring signals from the reset controller. On a 1G reconfig that always fail the status ends up: rc_busy = ‘1’ , rx_is_lockedtodata_out = ‘0’, pll_locked = ‘1’, tx_analogreset = ‘0’, rx_analogreset= ‘0’, tx_digitalreset=’0’, rx_digitalreset=’1’, tx_cal_busy=’0’, rx_cal_busy=’0’

I'm looking for debug suggestions and/or implementation ideas (that don't use a 125MHz oscillator).

Thanks.

  • jsenesi's avatar
    jsenesi
    5 years ago

    Hi dlim,

    I have found a solution working in the lab. For some reason generating the 125MHz from 644MHz with an IOPll seems to work, while using an fPLL has not.

    I have attached a new clock diagram illustrating.

    Regards,

    Joe

4 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,

    Pls see my comment below

    1. Regarding 1G/10G PHY IP clocking clarification
    2. Regarding 1G operation stuck in calibration process issue

    Thanks.

    Regards,

    dlim

    • jsenesi's avatar
      jsenesi
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi,

      I've attached an illustration of my clocking. The notable difference is the lack of a 125MHz reference clock and my using the 644.53125 with cascaded fPLLs to generate 1GbE references.

      I will look at the reference design and see if there are any other differences I should be concerned about.

      Thanks,

      Joe

      • Deshi_Intel's avatar
        Deshi_Intel
        Icon for Regular Contributor rankRegular Contributor
        5 years ago

        Hi Joe,

        Thanks for sharing your design clocking diagram.

        Yup, the difference is mainly on 1G clocking side.

        • Cascading fPLL is not recommended due to higher jitter affecting the clock network performance.
        • Also, I am not sure how you connect 1G CDR (rx_cdr_refclk_1g) in your design. Based on reference design, this should be using same 125MHz clock source to clock both 1G Tx_PLL and 1G Rx_CDR

        Thanks.

        Regards,

        dlim