Forum Discussion
New Contributor1G/10G PHY single reference clock
Hi dlim,
I have found a solution working in the lab. For some reason generating the 125MHz from 644MHz with an IOPll seems to work, while using an fPLL has not.
I have attached a new clock diagram illustrating.
Regards,
Joe
Regular ContributorHI,
Pls see my comment below
- Regarding 1G/10G PHY IP clocking clarification
- A10 PHY user guide doc (page 168, figure 75) show you clocking explanation where it uses fPLL/CMU PLL for 1G PMA, ATX PLL/CMU PLL for 10G PMA and another fPLL for PCS clocking
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf
- Sorry but it's not clear to me how you implement the clocking design at your side. Can you explain exactly how does it differ from figure 75
- Regarding 1G operation stuck in calibration process issue
- I am not sure whether your 1G/10G PHY IP is connected and configured correctly or not.
- Why not you generate a working 1G/10G PHY IP design example from "A10 low latency Ethernet 10G MAC IP" and then cross check with your own design ?
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20016.pdf (refer to chapter 3)
Thanks.
Regards,
dlim
jsenesiHi,
I've attached an illustration of my clocking. The notable difference is the lack of a 125MHz reference clock and my using the 644.53125 with cascaded fPLLs to generate 1GbE references.
I will look at the reference design and see if there are any other differences I should be concerned about.
Thanks,
Joe
- Deshi_Intel
Hi Joe,
Thanks for sharing your design clocking diagram.
Yup, the difference is mainly on 1G clocking side.
- Cascading fPLL is not recommended due to higher jitter affecting the clock network performance.
- Also, I am not sure how you connect 1G CDR (rx_cdr_refclk_1g) in your design. Based on reference design, this should be using same 125MHz clock source to clock both 1G Tx_PLL and 1G Rx_CDR
Thanks.
Regards,
dlim
- jsenesi
Hi dlim,
I have found a solution working in the lab. For some reason generating the 125MHz from 644MHz with an IOPll seems to work, while using an fPLL has not.
I have attached a new clock diagram illustrating.
Regards,
Joe
