Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

1-wire (onewire) SOPC builder component

Hi,

Project home:

http://opencores.org/project,sockit_owm

The source code is here:

https://github.com/jeras/sockit_owm

The GitHub version might be temporarily slightly ahead to the OpenCores version.

RTL features:

- small RTL, should fit into a CPLD

- Avalon MM bus, Wishbone compatible with a simple adapter

- timed reset, presence, write/read bit transfers

- overdrive

- power supply (strong pull-up)

SOPC Builder integration

Nios II EDS integration:

- port of the 1-wire open domain kit version 3.10b

- interrup driven or polling driver

- uCOS-II support (only partialy tested)

Known issues:

- there is no automatic detection of uCOS-II so:

-- with HAL only the polling driver works properly

-- with uCOS-II the interrupt driven driver should be used (polling disabled)

I would appreciate questions and bug reports.

Note: Tar with the component was updated to Rev 5 from OpenCores.org, equivalent to hash a8dfa48 on GitHub.com

Regards,

Iztok Jeras

15 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I have the latest version that you recommended. There is not a huge rush, so I will wait for you to check out your driver in Qsys. I need to use the current version of Quartus and Qsys, and I figure that getting it to work with the latest software is a good plan regardless.

    Again, thank you for your help.

    - Curtis
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Curtis,

    I started with a fresh project for the DE1 board and was able to build it hardware and run the software. I did not encounter the same problem you did, I copied the sockit_owm directory inside the Quartus project directory, so I do not get what the problem with your project is.

    There is a small issue with clock calculation. When you add the sockit_owm component the tool will complain about a divide by zero, this error will go away as soon as a clock is connected to the component, I will try to add a check so that a more descriptive error would be given.

    I also encountered problems with the software. The default software configuration is with interrupts enabled. But it seems interrupts only work properly if UCOS-II is used. I have yet to find a proper fix for this issue. For now set the pooling driver option in the BSP editor.

    Regards,

    Iztok Jeras
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Iztok,

    I got it to compile. It turns out that I didn't have the sockit_owm directory inside the project directory. This seems to make a difference even if the Qsys IP search path is set to the sockit_owm directory.

    Thank you for your help. I will proceed and let you know if I run into other problems.

    Best,

    - Curtis
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Curtis,

    The "Qsys IP search path" should point to the parent directory of the components. For example if you have many custom made components inside one directory, you have to add a single path.

    Do you plan to use UCOS-II, or simply HAL?

    I am looking forward to your progress. I have spent a lot of time writing and testing this code, but is is hard to find other developers willing to test it.

    Regards,

    Iztok Jeras
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hello,

    Ich work with an Altera de0 Board an am Maxim DS2218. I have a One-Wire-Code from Maxim. I implemented to the SOPC Builder and now I must write an Avalon MM Master.

    How can I write it? can you help me?

    Regards