Xilinx fddrrse primitive

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Is there an Altera primitive to create an FDDRRSE?

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Probably. But providing a port map tells us absolutely nothing.

Explain what you are using the component for.

Cheers,

Dave

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Sorry, but I figured it out... I'm using the altddio_in MegaFunction.

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That was the component I was going to recommend :)

If your external signals are LVDS, then there are also altlvds_rx/tx components.

Cheers,

Dave

I do have one question about the altddio_out/altddio_in. I'm creating the altddio_out with a bit width of 1. The wizard generates a variation file with the following entity...

ENTITY sync_clk_ddr IS

PORT

(

datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

outclock : IN STD_LOGIC ;

dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

);

END sync_clk_ddr;

When I go to use this MegaFunction, it expects the data_in and data_out to be a vector. I'm trying to assign the data_out to a std_logic. Is there a way to convert froma std_logic_vector to std_logic?

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When I go to use this MegaFunction, it expects the data_in and data_out to be a vector. I'm trying to assign the data_out to a std_logic. Is there a way to convert froma std_logic_vector to std_logic?

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Yeah, use

dataout(0) <= dataout

where the signal dataout is std_logic.

Cheers,

Dave