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Altera_Forum
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14 years ago

Xilinx fddrrse primitive

Is there an Altera primitive to create an FDDRRSE? sync_clk_ddr : fddrrse port map ( Q => dds_sync_clk, C0 => clk_125, C1 => clk_125_inv, CE => '1', D0 => '1', D1 => ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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When I go to use this MegaFunction, it expects the data_in and data_out to be a vector. I'm trying to assign the data_out to a std_logic. Is there a way to convert froma std_logic_vector to std_logic?

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Yeah, use

dataout(0) <= dataout

where the signal dataout is std_logic.

Cheers,

Dave