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Altera_Forum
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14 years ago

Xilinx fddrrse primitive

Is there an Altera primitive to create an FDDRRSE? sync_clk_ddr : fddrrse port map ( Q => dds_sync_clk, C0 => clk_125, C1 => clk_125_inv, CE => '1', D0 => '1', D1 => ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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Is there an Altera primitive to create an FDDRRSE?

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Probably. But providing a port map tells us absolutely nothing.

Explain what you are using the component for.

Cheers,

Dave