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Altera_Forum
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14 years ago

Xilinx fddrrse primitive

Is there an Altera primitive to create an FDDRRSE? sync_clk_ddr : fddrrse port map ( Q => dds_sync_clk, C0 => clk_125, C1 => clk_125_inv, CE => '1', D0 => '1', D1 => ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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Sorry, but I figured it out... I'm using the altddio_in MegaFunction.

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That was the component I was going to recommend :)

If your external signals are LVDS, then there are also altlvds_rx/tx components.

Cheers,

Dave