Xilinx fddrrse primitive

I do have one question about the altddio_out/altddio_in. I'm creating the altddio_out with a bit width of 1. The wizard generates a variation file with the following entity...

ENTITY sync_clk_ddr IS

PORT

(

datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

outclock : IN STD_LOGIC ;

dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

);

END sync_clk_ddr;

When I go to use this MegaFunction, it expects the data_in and data_out to be a vector. I'm trying to assign the data_out to a std_logic. Is there a way to convert froma std_logic_vector to std_logic?