Forum Discussion
aiedb
Occasional Contributor
5 days agohii good morning , i found out something that got under my radar sort of speak , i built a qsys system with pll that feeds the on chip flash ip and the dual configuration ip , and my logic for reading and writing worked directly from the on board osc , so infact even if the clk is 50mhz the same .
the outputs from the pll and 50mhz from osc ,they are separate time domains i removed the pll from the design and worked with the on board osc clk only for my logic and for the altera ip and it worked i dont have any failures any more , i still need to test the design with reduced delay between the sent rpd words . i will check on that
JohnT_Altera
Regular Contributor
1 day agoThanks for update and glad that you are able move forward after resolving the issue
- aiedb1 day ago
Occasional Contributor
thanks for your help :)