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Honored Contributorwire the 16207 lcd to nios2 module
I have a EP3SL150 board and want to use the 16207 lcd on it with my nios2 processor! I already included the corresponding module in my sopc design and generated my processor.
Now i have to wire the lcd in my toplevel entity and here is the problem. In the manual from the development board i have the following 11 pins to connect: LCD_DATA0 2.5 V AJ8 LCD_DATA1 2.5 V AJ6 LCD_DATA2 2.5 V AD13 LCD_DATA3 2.5 V AJ7 LCD_DATA4 2.5 V AF10 LCD_DATA5 2.5 V AN6 LCD_DATA6 2.5 V AN3 LCD_DATA7 2.5 V AK7 LCD_D_Cn 2.5 V AP2 LCD_WEn 2.5 V AL8 LCD_CSn 2.5 V AD12 It is clear how to connect the 8 data pins, but the names of the other three are quite strange because the output signals of the sopc module are named: LCD_E_from_lcd_6 LCD_RS_from_lcd_6 LCD_RW_from_lcd_6 Maybe there is somebody who knows how to connect the pins corretly! I also have the problem that i get some Warnings while Quartus Synthesis because of the 8 DATA Signals, because this Signals are bidirectinal (inout) and are just used as output! The Warning looks like this: Warning: Inserted always-enabled tri-state buffer between "LCD_data_to_and_from_lcd_6[7]" and its non-tri-state driver Warning: TRI or OPNDRN buffers permanently enable3 Replies
Altera_ForumIt looks ok... check that you assigned the correct pins to those signals (prefferably using the board schematics rather than the documentation).
You can also put some SignalTap probes to see if you are driving the LCD correctly.- Altera_Forum
i have now wired the pins as you sayed but it is still not working :(
i now think that the main problem are the data pins which should be inout. Maybe i did indeed something wrong in my toplevel file. i don't know what it is because for me it looks quite ok! :) here is my toplevel file:library IEEE; use IEEE.std_logic_1164.all; use work.noctypes.all; entity canrouter is port ( -- global signals clkin_50 : in std_logic; -- clock input, 50 MHz user_resetn : in std_logic; -- user reset -- the lcd display LCD_E_from_lcd_6 : out std_logic; LCD_RS_from_lcd_6 : out std_logic; LCD_RW_from_lcd_6 : out std_logic; LCD_data_to_and_from_lcd_6 : inout std_logic_vector(7 DOWNTO 0); -- the_uart_0 rxd_to_uart_0 : in std_logic; -- uart rxd txd_from_uart_0 : out std_logic; -- uart txd -- the_uart_1 rxd_to_uart_1 : in std_logic; -- uart rxd txd_from_uart_1 : out std_logic; -- uart txd -- the_uart_2 rxd_to_uart_2 : in std_logic; -- uart rxd txd_from_uart_2 : out std_logic; -- uart txd -- the_uart_3 rxd_to_uart_3 : in std_logic; -- uart rxd txd_from_uart_3 : out std_logic; -- uart txd -- the_uart_4 rxd_to_uart_4 : in std_logic; -- uart rxd txd_from_uart_4 : out std_logic -- uart txd ); end canrouter; architecture structural of canrouter is signal wsysclk : std_logic; signal wmtclk : std_logic; signal wUNI_in : vt_uni_in(6 downto 0); signal wUNI_out : vt_uni_out(6 downto 0); begin -------------------------------------------------------------------------------- -- macro tick generation -------------------------------------------------------------------------------- mtgen_inst : entity work.mtgen(behavioural) generic map ( CNT_VALUE => 953, ITER_VALUE => 4 ) port map ( clk => wsysclk, mtclk => wmtclk, reset_n => user_resetn ); -------------------------------------------------------------------------------- -- component instance of network-on-chip -------------------------------------------------------------------------------- noc_inst : entity work.noc(structural) -- noc_inst : component noc generic map ( NROFTISS => 7, ROWS => 1, COLS => 3, INTERCONNECTS => 4, MEMINIT_DIR => "../meminit/" ) port map ( UNI_in => wUNI_in, UNI_out => wUNI_out, FS_Enable => (others=>'1'), clk => wsysclk, mtclk => wmtclk, reset_n => user_resetn ); -------------------------------------------------------------------------------- -- component instance of SOPC Component -------------------------------------------------------------------------------- sopc_inst : entity work.userland(europa) -- sopc_inst : component work.userland port map ( -- the_avalon_tiss_0 CIAddr_from_the_avalon_tiss_0 => wUNI_in(0).CIAddr, CINameSpace_from_the_avalon_tiss_0 => wUNI_in(0).CINameSpace, CIRDData_to_the_avalon_tiss_0 => wUNI_out(0).CIRDData, CIRDEna_from_the_avalon_tiss_0 => wUNI_in(0).CIRDEna, CIWRData_from_the_avalon_tiss_0 => wUNI_in(0).CIWRData, CIWREna_from_the_avalon_tiss_0 => wUNI_in(0).CIWREna, PIAddr_to_the_avalon_tiss_0 => wUNI_out(0).PIAddr, PIMemErr_from_the_avalon_tiss_0 => wUNI_in(0).PIMemErr, PIRDData_from_the_avalon_tiss_0 => wUNI_in(0).PIRDData, PIRDEna_to_the_avalon_tiss_0 => wUNI_out(0).PIRDEna, PIWRData_to_the_avalon_tiss_0 => wUNI_out(0).PIWRData, PIWREna_to_the_avalon_tiss_0 => wUNI_out(0).PIWREna, SBMasterInt_to_the_avalon_tiss_0 => wUNI_out(0).SBMasterInt, -- the_avalon_tiss_1 CIAddr_from_the_avalon_tiss_1 => wUNI_in(1).CIAddr, CINameSpace_from_the_avalon_tiss_1 => wUNI_in(1).CINameSpace, CIRDData_to_the_avalon_tiss_1 => wUNI_out(1).CIRDData, CIRDEna_from_the_avalon_tiss_1 => wUNI_in(1).CIRDEna, CIWRData_from_the_avalon_tiss_1 => wUNI_in(1).CIWRData, CIWREna_from_the_avalon_tiss_1 => wUNI_in(1).CIWREna, PIAddr_to_the_avalon_tiss_1 => wUNI_out(1).PIAddr, PIMemErr_from_the_avalon_tiss_1 => wUNI_in(1).PIMemErr, PIRDData_from_the_avalon_tiss_1 => wUNI_in(1).PIRDData, PIRDEna_to_the_avalon_tiss_1 => wUNI_out(1).PIRDEna, PIWRData_to_the_avalon_tiss_1 => wUNI_out(1).PIWRData, PIWREna_to_the_avalon_tiss_1 => wUNI_out(1).PIWREna, SBMasterInt_to_the_avalon_tiss_1 => wUNI_out(1).SBMasterInt, and so on............ -- the_avalon_tiss_6 CIAddr_from_the_avalon_tiss_6 => wUNI_in(6).CIAddr, CINameSpace_from_the_avalon_tiss_6 => wUNI_in(6).CINameSpace, CIRDData_to_the_avalon_tiss_6 => wUNI_out(6).CIRDData, CIRDEna_from_the_avalon_tiss_6 => wUNI_in(6).CIRDEna, CIWRData_from_the_avalon_tiss_6 => wUNI_in(6).CIWRData, CIWREna_from_the_avalon_tiss_6 => wUNI_in(6).CIWREna, PIAddr_to_the_avalon_tiss_6 => wUNI_out(6).PIAddr, PIMemErr_from_the_avalon_tiss_6 => wUNI_in(6).PIMemErr, PIRDData_from_the_avalon_tiss_6 => wUNI_in(6).PIRDData, PIRDEna_to_the_avalon_tiss_6 => wUNI_out(6).PIRDEna, PIWRData_to_the_avalon_tiss_6 => wUNI_out(6).PIWRData, PIWREna_to_the_avalon_tiss_6 => wUNI_out(6).PIWREna, SBMasterInt_to_the_avalon_tiss_6 => wUNI_out(6).SBMasterInt, -- 1) global signals: clk_50 => clkin_50, sysclk => wsysclk, reset_n => user_resetn, -- the_lcd_display_6 LCD_E_from_the_lcd_6 => LCD_E_from_lcd_6, LCD_RS_from_the_lcd_6 => LCD_RS_from_lcd_6, LCD_RW_from_the_lcd_6 => LCD_RW_from_lcd_6, LCD_data_to_and_from_the_lcd_6(7 downto 0) => LCD_data_to_and_from_lcd_6(7 downto 0), -- the_uart_0 rxd_to_the_uart_0 => rxd_to_uart_0, txd_from_the_uart_0 => txd_from_uart_0, -- the_uart_1 rxd_to_the_uart_1 => rxd_to_uart_1, txd_from_the_uart_1 => txd_from_uart_1, -- the_uart_2 rxd_to_the_uart_2 => rxd_to_uart_2, txd_from_the_uart_2 => txd_from_uart_2, -- the_uart_3 rxd_to_the_uart_3 => rxd_to_uart_3, txd_from_the_uart_3 => txd_from_uart_3, -- the_uart_4 rxd_to_the_uart_4 => rxd_to_uart_4, txd_from_the_uart_4 => txd_from_uart_4 ); end structural; - Altera_Forum
I think that you should connect them like that:[list][*]LCD_E_from_lcd_6 -> LCD_CSn[*]LCD_RW_from_lcd_6 -> LCD_WEn[*]LCD_RS_from_lcd_6 -> LCD_D_Cn[/list]
You should define your data signals as bidirectionnal on the top level file too, because they are also used as inputs to read the LCD's controller's status.
