why PLL miss output port?

Hi sstrell, thank you very much.

I'm sure that I had enabled CLK[4] because TimeQuest can analysis the timing of CLK[4] in case(2), and the Verilog model file also define that it's used, like following picture.

verilog file of PLL:

Could you please tell me what clock control block IP can be used for clock network switching in case(1)?

Hi Ash_R_Intel, thank you very much.

I need a MUX to switch the clock between normal mode and test mode. So, I don't care about any transient state when clock switching. Under the case(1), 'pll_c4_sw' is the switched output clock. Some IP use 'pll_c4_sw' this clock. 'pll_c4' is the clock from PLL under test mode when the 'sel' signal is 1. 'clk_pin' is the input clock from other device via normal FPGA pin and pin function selection function (combinational circuit) when the 'sel' signal is 0.

Unfortunately, Quartus13.1 tell me that "PLL "pll|altpll_component|auto_generated|pll1" has parameters clk4_multiply_by and clk4_divide_by specified but port CLK[4] is not connected." when I use the Stratix III device under the case(1).

Do you have any idea about this case? If you have some idea, could you please tell me? Thank you very much.

Case(1):

assign pll_c4_sw = sel? pll_c4 : clk_pin;