Forum Discussion
NuvKFC
Contributor
Contributorwhy PLL miss output port?
I have a warning message that I don't why it appear. I use ALLPLL to generate other clocks. The output of PLL is from pll_c0 to pll_c5. Following's case are the case that I had tried at pll_c4.
Ca...
sstrell
Super Contributor
Super ContributorIt looks like you didn't enable CLK[4] in the PLL's parameter editor.
But also for your "case 1", you should use a clock control block IP to do clock network switching instead of this.
NuvKFCContributor
ContributorHi sstrell, thank you very much.
I'm sure that I had enabled CLK[4] because TimeQuest can analysis the timing of CLK[4] in case(2), and the Verilog model file also define that it's used, like following picture.
verilog file of PLL:
Could you please tell me what clock control block IP can be used for clock network switching in case(1)?
