Why i can not setting for PLL?

Question

hi everybody, I have project with FPGA board DE2, cyclone 2 EP2C35F672C6. But when i config for PLL in megafunction it is error. Why??? This is the step that i confog for my PLL.

altera_forum · Answer

Hello,

PLLs have limitations.

You are requesting a PLL that takes a 50 MHz clock input and produces both a 500 MHz output and a 400 MHz output.

That particular combination is outside the PLL's capabilities.

More information at http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf

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Why i can not setting for PLL?

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