Forum Discussion
8 Replies
- Altera_Forum
Honored Contributor
I had a similar discussion a few years back. The trouble is, what to _you_ consider a middle performance ADC? 10-bit at 100KHz? 12-bit at 1MHz?
Audio people will want more bits but lower update rates, video people will want fewer bits but high update rates, industrial people will be all over the place. Bo matter what ADC will go into the MAX2, the audience will always find the solution bad ;-) - Altera_Forum
Honored Contributor
No such a idea is well for anyone.
Good product defination can get enough ROI. And I think accuracy(X bits) is related to die size, sample rate is related to silicon process performance. Based on current MAXII fmax performance, I also think sample rate performance should not be Altera's problem. Just the balance between accuracy/market coverage vs die size/cost - Altera_Forum
Honored Contributor
Customer,price
- Altera_Forum
Honored Contributor
- Altera_Forum
Honored Contributor
Beside what has been mentioned, I doubt a fair number of significant bit is possible when the high currents inside a CPLD are switching. The ADC manufacturer hint that the ADCs need to be connected to the analog GND, which clearly is not the GND where the CPLD is on.
Rene - Altera_Forum
Honored Contributor
I think, the best thing Altera can do is to supply ip interfaces to common ADC's to assist the user and to collaborate with adc vendors on new interface architectures.
Note, its not so many years ago the ADC's got LVDS ports simplifying gnd separation. Also we now see adc's with built-in test pattern generators which are very useful to verify the timing and integrity of the board. I have yet to see an adc with JTAG test port features! I wonder when ADC's which fits seamlessly into an Altera SERDES port will appear? Would be nice though. - Altera_Forum
Honored Contributor
See this:
http://www.alteraforum.com/forum/showthread.php?p=775#post775 regards Daniel - Altera_Forum
Honored Contributor
Maybe very few people have such requirement