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Altera_Forum
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19 years ago

Why Altera do not integrate ADC into CPLD?

Engineers welcome the integrated solution. It do help to save board size and save time on developing and debug work. As the CPLD performance is limited, so middle performance ADC is enough for C...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

No such a idea is well for anyone.

Good product defination can get enough ROI.

And I think accuracy(X bits) is related to die size, sample rate is related to silicon process performance.

Based on current MAXII fmax performance, I also think sample rate performance should not be Altera's problem.

Just the balance between accuracy/market coverage vs die size/cost