Where is the "dedicated clock output pin" of Cyclone II FPGA?

Hi,

I am now using a customed Cyclone II Evaluation Module. The FPGA is EP2C8Q208C8.

I managed to use the ALTPLL module to generate a 150MHz clock signal. Meanwhile, the clock signal would be output to a DAC IC. By assigning the 150M-clock-output into a GPIO, I received a warning from Quartus II : "...Use PLL dedicated clock outputs to ensure jitter performance". I do know there were dedicated clock output for each PLL. However, I don't know which pin it is. Although I tried to search the "dedicated clock output pin" in cyclone ii handbook, the result seems meaningless for me.

Could you please tell me which pin in EP2C8Q208C8 is the "dedicated clock output" for PLL1?

Naroah

Feb/22/2014