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Honored Contributor
Honored ContributorWhere is the "dedicated clock output pin" of Cyclone II FPGA?
Hi, I am now using a customed Cyclone II Evaluation Module. The FPGA is EP2C8Q208C8. I managed to use the ALTPLL module to generate a 150MHz clock signal. Meanwhile, the clock signal wou...
Altera_ForumHonored Contributor
Honored ContributorYou find the answer in the Quartus pin planner tool or the device pinout files. PLL1_OUTp is pin 47 of Q208 package.
