Where can I find clock mux?

Question

Hi, everyone.

In my project, 2M,4M,8M and 16M bitstreams will be transived to the reciver. For the reciver, it must know the clock which the bitstream contains. The cyclones have no DPA or CDR, so i have to supply clock at the reciver(when the sender gives 2M bitstreams , according to the process I write, the reciver will know the rate of the bits, so it can provide the clock by itself).

The rate of the data are changing per every 125us, the clock at the reciver will change too,so it can recive the data properply,where can i find the clock mux in quartus to change the clock? And the way i described can be OK?

Please. Thanks very much.

altera_forum · Answer

I'm assuming all the clocks are related(basically edge-aligned) just at lower rates. Do the same thing in the FPGA, i.e. drive it with the 16MHz clock. If getting 16Mbit data, then have that domain always enabled. If receiving 8Mbit data, then drive the clock enable of the logic with a divide-by-2 register. For 4M, then drive it with a clock enable that is high every 4th cycle. The only thing you need to be sure of is that the edge you enabled corresponds with the center of the data eye.

Another option, depending on the architecture, is to use a PLL to create all the frequencies you want, and then use the altclkctrl megafunction to mux between them.

What you're probably tempted to do is build a mux out of the general logic fabric, and just choose them that way. In general, you want to avoid this since your clocks are now on general routing channels which are not low-skew, and you have to worry about hold times and what not. The frequencies are slow enough that it should all be doable, but in general you want to stay away from gating clocks in the fabric.

altera_forum · Answer

Thank you very much,Rysc.

Compared to the first way you stated, I think the other one may run at higher speed. Use pll to create all the frequencies i need, but the pll only can create 3 frequencies sometimes only two different frequencies . I need four different frequencies used as clock, can I use more than one Pll to create the clock i need ? (Of course the input clock is the same one)

In my opinion (if i understand you correctly)what your suggestion is to avoid the design fabric as i described in my post, is it?

In order to get a higher speed such as more than 400M , I can't find a better way to deal with the problerm i mentioned on my post with the cyclone series.

altera_forum · Answer

Either way generally works. The clock enable method is good because it only uses one true system clock(and you can use PLL outputs for other stuff), but the PLL -> Altclkcntrl solution tends to be easier.

For clarification, your original data rates were 2M-16M, which I took to mean a 16MHz clock or lower, but in this latest post you say 400M, which is a whole different ballgame. What's the fastest rate you'll have? Also, are all the clocks truly related, i.e. generated from the same source? Neither of these solutions work if, for example, the 8Mbit and 16Mbit data sources come from different clock sources, as they vary slightly over time, and that variance will add up. (Just like you can't feed data from one clock source to another clock source, even if they're listed as the same rate, because they won't be exactly, and your system needs to be able to add comma characters and/or let them slip.)

altera_forum · Answer

Thanks , Rysc. I have two parts in my design. One is the transmitter, which will pack the data at 2M-16M. The other is the receiver , which recives the changed-speed data and then pack the recived data at higher speed datastream(such as 32M or higher).

For the reciver, before writing the data into FIFO , sampling-correctly is needed, so i must know the clock of the transmitter, problerm is that i can't get the clock from the transmitter, i have to create new clock to sample the data from the transmitter.

For the transmitter, the clocks are generated from the same clock source, the speed of the data sources change from 2 to 16M.

The focus is how the created clock sample the data correctly , stable sampling is badly needed. Altclkcntrl solution tends to be much better. So , what about your ideas?

Thanks very much.

altera_forum · Answer

I didn't answer yet cause the system characteristics seems to vague to me, particulary the possible reference clock source wasn't even mentioned. It's still unclear from your last post.

If the maximum data rate is below 100 Mbit/s, a UART design could be a solution. You sample the incoming data at high speed in a deserializer (e. g. 400 MHz is no problem with Cyclone II or III) and extract clock phase and data from the bit stream, provided that any synchronization or start pattern exist (it obviously must for an operational protocol). In such a design, the rate change would be achieved in the decoding of deserializer output, that should operate at a slow clock.

At a suitable low speed, you can achieve an equivalent to DPA in logic cells, without using a "tapped" PLL as real DPA does. A synchronization must be achieved somehow anyway.

The unclear point is, what create new clock to sample the data means. If it's from the same clock oscillator as transmitter with unknown phase, you only need phase align, but if has also a frequency offset, permanent resynchronization is needed. DPA e. g. wouldn't be able to handle it, cause simple synchronous serial transmission has no guaranteed edges and would loose synchronization after a short time. The solution can be either an UART like protocol or a protcol like 8b10 encoding with guaranteed edges and embedded unique comma characters.

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Where can I find clock mux?

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