Where can I find clock mux?

I'm assuming all the clocks are related(basically edge-aligned) just at lower rates. Do the same thing in the FPGA, i.e. drive it with the 16MHz clock. If getting 16Mbit data, then have that domain always enabled. If receiving 8Mbit data, then drive the clock enable of the logic with a divide-by-2 register. For 4M, then drive it with a clock enable that is high every 4th cycle. The only thing you need to be sure of is that the edge you enabled corresponds with the center of the data eye.

Another option, depending on the architecture, is to use a PLL to create all the frequencies you want, and then use the altclkctrl megafunction to mux between them.

What you're probably tempted to do is build a mux out of the general logic fabric, and just choose them that way. In general, you want to avoid this since your clocks are now on general routing channels which are not low-skew, and you have to worry about hold times and what not. The frequencies are slow enough that it should all be doable, but in general you want to stay away from gating clocks in the fabric.