Where can I find clock mux?

Thanks for clarifying. This the case of unknown clock phase, as it could be handled by DPA hardware. It needs a train pattern and a synchronisation phase or a protocol with unique synchronisation pattern, as HDLC and a clock phase synchronisation at the receiver. Thus I would empasize my suggestion of oversampling the input data and create a "software DPA". I can hardly imgagine how the data should be recovered otherwise. This is functionally the same as Rysc suggested, but with additional oversampling.