Thanks , Rysc. I have two parts in my design. One is the transmitter, which will pack the data at 2M-16M. The other is the receiver , which recives the changed-speed data and then pack the recived data at higher speed datastream(such as 32M or higher).
For the reciver, before writing the data into FIFO , sampling-correctly is needed, so i must know the clock of the transmitter, problerm is that i can't get the clock from the transmitter, i have to create new clock to sample the data from the transmitter.
For the transmitter, the clocks are generated from the same clock source, the speed of the data sources change from 2 to 16M.
The focus is how the created clock sample the data correctly , stable sampling is badly needed. Altclkcntrl solution tends to be much better. So , what about your ideas?
Thanks very much.