Where can I find clock mux?

I didn't answer yet cause the system characteristics seems to vague to me, particulary the possible reference clock source wasn't even mentioned. It's still unclear from your last post.

If the maximum data rate is below 100 Mbit/s, a UART design could be a solution. You sample the incoming data at high speed in a deserializer (e. g. 400 MHz is no problem with Cyclone II or III) and extract clock phase and data from the bit stream, provided that any synchronization or start pattern exist (it obviously must for an operational protocol). In such a design, the rate change would be achieved in the decoding of deserializer output, that should operate at a slow clock.

At a suitable low speed, you can achieve an equivalent to DPA in logic cells, without using a "tapped" PLL as real DPA does. A synchronization must be achieved somehow anyway.

The unclear point is, what create new clock to sample the data means. If it's from the same clock oscillator as transmitter with unknown phase, you only need phase align, but if has also a frequency offset, permanent resynchronization is needed. DPA e. g. wouldn't be able to handle it, cause simple synchronous serial transmission has no guaranteed edges and would loose synchronization after a short time. The solution can be either an UART like protocol or a protcol like 8b10 encoding with guaranteed edges and embedded unique comma characters.