What's the maximum input current of 3.3V LVTTL for Cyclone4?

We are using the EP4CE10 for our new design, but ever time the QII complie the design, we get the Warning (169177): 18 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.

So, we read the AN 447 carefully. In our design, we wan to use 3.3V for boh EP4CE10 and it's interface chips such as SRAM and FLASH. But we cann't get the maximum output current value for SRAM and FLASH, and because there are too many pins connected to SRAM and FLASH, using the series termination method is too complex!

If know the maximum input current value of 3.3V LVTTL pin for EP4CE10, we can make choice to add series termination or not.

Anyone knows about it???

It seems like you misunderstood the meaning of the maximum input current rating. In normal operation, when driven from a 3.3V driver, the FPGA input current, with or without PCI diode, is about zero, except for uA level leakage currents. PCI diodes are placed to clamp dynamical signal overshoots, the 10 mA rating specifies the allowed current when continuously drving the input from an output of higher output level.

When designing series termination, you can assume zero input current of LVCMOS/LVTTL FPGA inputs. External chips can have an input current if they are fabricated in bipolar technlogy, but these days, most are CMOS as well.

Thanks for your reply, FvM.

May be we can define the maximum FPGA input current rating for dynamical overshoots, with PCI diode, is 10 mA, that's right? If so, we should limit the driver maximum output current the same as this value, without series termination.

But, in AN447 Table 3, give the Maximum Allowed Current from driver is 30-mA for a 3.3V to 3.3V interface without series termination, this value is much more than the allowed 10 mA PCI diode current limit.

So mysterious extra current! May be it's to control the overshoot voltage at the FPGA input pin not exceed the PCI diode's foward voltage condition when driver a 50ohm transmission line, if so, there is no need to enable the FPGA input pin's PCI diode, that's right?

The 10 mA rating is a DC value, not the overshoot peak current. The point is discussed in AN447:

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10-mA DC current limit refers to the current that the diode sinks and not the drive strength of the driver. This limit is only applicable when the PCI-clamp diode is enabled and when the 2.5-V Cyclone III and Cyclone IV device receiver interfaces with 3.0-V or 3.3-V LVTTL/LVCMOS I/O systems.

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In my opinion, you should preferably adjust FPGA driver strengths accordingly and use series termination with other chips to avoid overshoots instead of relying on the PCI diode clamping the input voltage.