What is wrong with this code?

LIBRARY altera;

USE altera.maxplus2.ALL;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY test IS

PORT

(

a, b, c, gn : IN STD_LOGIC;

d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

y, wn : OUT STD_LOGIC

);

END test;

ARCHITECTURE a OF test IS

BEGIN

mux : a_74151b PORT MAP (c, b, a, d, gn, y, wn);

END a;

Warning: LMF mapping record a_74151b -> 74151b missing the "mux" port mapping(s) for node "mux"

Error: Node instance "mux" instantiates undefined entity "a_74151b"

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 9 warnings

Error: Quartus II Full Compilation was unsuccessful. 1 error, 9 warnings

I use QuartusII 9.1 and port map a_74151 is ok.

LIBRARY altera;

USE altera.maxplus2.ALL;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY test IS

PORT

(

a, b, c, gn : IN STD_LOGIC;

d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

y, wn : OUT STD_LOGIC

);

END test;

ARCHITECTURE a OF test IS

BEGIN

mux : a_74151 PORT MAP (c, b, a, d(7),d(6),d(5),d(4),d(3),d(2),d(1),d(0), gn, y, wn);

END a;