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Altera_Forum
Honored Contributor
Honored ContributorWhat is wrong with this code?
LIBRARY altera; USE altera.maxplus2.ALL; LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY test IS PORT ( a, b, c, gn : IN STD_LOGIC; d : IN STD_LOGIC_VECTOR(7 DOWN...
Altera_ForumHonored Contributor
Honored ContributorIf you use VHDL'93 coding standard you do not need to include a package or declare the component.
Just google for "VHDL'93 instantiation style"
