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Altera_Forum's avatar
Altera_Forum
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9 years ago

What is VHDL equivalent for Verilog $readmemb to initilze RAM/ROM?

The $readmemb() is mentioned in "Recommended Coding Styles" page 12-26. It seems that this can be used in simulation AND synthesis.

If one unfortunately uses VHDL rather than Verilog, than how does one initialize the RAM/ROM? The idea is to write code such that it gets inferred as the correct type of memory block AND be initilized usign the required content from a MIF file. In other words, it must synthesize.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Unfortunately, Altera has decided not to support what would be the most obvious replacement - the textio package (Xilinx Supports it).

    That means the only ways to support mem init in synthesis are:

    1. Use a constant and initialise the ram signal in the code:

    signal my_ram_sig : my_ram_type := MEM_INIT_CONSTANT;

    2. Use a mem init function: 

    
function mem_init_function return ram_t is
  variable ret : ram_t;
begin
  for i in ret'range loop
    ret(i) := --some calculated value!
  end loop;
  return ret;
end function;
signal my_ram_sig : my_ram_type := mem_init_function;

    3. Use attributes as an init to the ram (either in code or via project assignments) 

    
type mem_t is array(0 to 255) of unsigned(7 downto 0);
signal ram : mem_t;
attribute ram_init_file : string;
attribute ram_init_file of ram :
signal is "my_init_file.mif";

    The only issue with 3. is that it wont initialise in simulation.

    For simulation of method three, you could write a function to read the mif file to init the contents.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    You are implying that I write a package that is automatically generated from a differnet programming language, this package shall contain the memory initialization function with the raw data.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    No, that would seem a little overkill. How do you need to initialise the ram? do you already have a .mif file? Could you just generate the data easily with a function? Why do you really need to initialise it at all?

    If you use the altsyncram component, you can specify a .mif file to use, and it will work in both simulation and synthesis.