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Altera_Forum
Honored Contributor
Honored ContributorWhat is VHDL equivalent for Verilog $readmemb to initilze RAM/ROM?
The $readmemb() is mentioned in "Recommended Coding Styles" page 12-26. It seems that this can be used in simulation AND synthesis. If one unfortunately uses VHDL rather than Verilog, than how...
Altera_ForumHonored Contributor
Honored ContributorNo, that would seem a little overkill. How do you need to initialise the ram? do you already have a .mif file? Could you just generate the data easily with a function? Why do you really need to initialise it at all?
If you use the altsyncram component, you can specify a .mif file to use, and it will work in both simulation and synthesis.
