What is VHDL equivalent for Verilog $readmemb to initilze RAM/ROM?

Unfortunately, Altera has decided not to support what would be the most obvious replacement - the textio package (Xilinx Supports it).

That means the only ways to support mem init in synthesis are:

1. Use a constant and initialise the ram signal in the code:

signal my_ram_sig : my_ram_type := MEM_INIT_CONSTANT;

2. Use a mem init function:

function mem_init_function return ram_t is
  variable ret : ram_t;
begin
  for i in ret'range loop
    ret(i) := --some calculated value!
  end loop;
  return ret;
end function;
signal my_ram_sig : my_ram_type := mem_init_function;

3. Use attributes as an init to the ram (either in code or via project assignments)

type mem_t is array(0 to 255) of unsigned(7 downto 0);
signal ram : mem_t;
attribute ram_init_file : string;
attribute ram_init_file of ram :
signal is "my_init_file.mif";

The only issue with 3. is that it wont initialise in simulation.

For simulation of method three, you could write a function to read the mif file to init the contents.