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Honored Contributor
Honored ContributorWhat is VHDL equivalent for Verilog $readmemb to initilze RAM/ROM?
The $readmemb() is mentioned in "Recommended Coding Styles" page 12-26. It seems that this can be used in simulation AND synthesis. If one unfortunately uses VHDL rather than Verilog, than how...
Altera_ForumHonored Contributor
Honored ContributorYou are implying that I write a package that is automatically generated from a differnet programming language, this package shall contain the memory initialization function with the raw data.
