What is the processing speed limitation of Cyclone IV E with speed grade C7?

Hi Michael,

Yes, the LVDS receiver is rated to 740Mbps (note: Mbps, not MHz).

So assuming you run the LVDS receiver in x7 mode, the data will enter the FPGA at ~105MHz. The ADC could be run at ~52MHz.

Unfortunately the scheme of using two LVDS receivers out-of-phase will not work. The issue will be that you cannot improve the setup/hold time of the receivers.

Adding an external clocked multiplexer would be a lot more trouble that its worth. I'd recommend starting out with the AFE operated at say 50MHz.

Would that be ok for your project?

Once you get the part operating at 50MHz, there is nothing to stop you from 'overclocking' your FPGA. You might be lucky and find that your board works fine at 910Mbps.

Cheers,

Dave

Hi Dave,

Yes, the speed grade for DE2-115 is C7, hence the LVDS receiver only goes up to 740MHz. (Table 1–36 (p466) of the latest Cyclone IV handbook), am i right?

I will first run the part with a lower frequency during the test. I know having a higher speed grade FPGA will probably fix all these speed issues, but i've already purchased the tPad(LCD + DE2-115)(costed me USD 850.00) for my senior design using my own money, so switching FPGA is probably not an option for me.

So back to my previous question. If i use 2 HSMC ports(all together 4 I/O) to receive the same LVDS signal, and my shift registers(14bits + 14bits) defined in verilog are running at half the speed of the LVDS signal. One group (14 bits) shift registers are triggered on the rising edge, while the other group (14 bits) shift registers are triggered on the falling edge.

In another words, i want the 2 HSMC ports to catch the LVDS data stream in alternate turns, to overcome the speed limitation issues. Do you think this approach will work? if no, what do you think is the limiting factor?

Thanks professor!

Regards,

Michael

The Cyclone IV handbook indicates 875 Mbps Rx for LVDS. Where did 'the speed limitation of DE2-115 (for HSMC) is 740MHz' come from (lower speed grade part perhaps)?

If the data from the ADC is 910Mbps, then I assume you are running the AFE at 14-bits, 910Mbps/14-bits = 65Msps. You could try running the part in 12-bit mode, 12*65 = 780Mbps, or you can reduce the 65MHz clock to something that your tests can handle.

If you absolutely have to run the part at 910Mbps, then you will need to get an evaluation board with faster LVDS receivers.

Keep in mind that you first need to evaluate and understand parts before going off and designing a board, or applying the device in your final application. There should be nothing wrong with operating the AFE at a lower frequency initially to learn how to use the part.

Note that the TI TW3100 board has a Stratix II device on it. Perhaps that board has an adapter to interface to the AFE evaluation board.

http://focus.ti.com/docs/toolsw/folders/print/tsw3100evm.html

Ouch! $3499. Ok, so maybe not! The Terasic DE3 and DE4 boards would probably be a better bet then.

Cheers,

Dave

Hi Dave,

The LVDS output from the ADC (TI's AFE5808) i am trying to receive, runs at 910 Mbps, and i am trying to deserialize the serial data from LVDS using DE2-115.

Since i know the speed limitation of DE2-115 (for HSMC) is 740MHz, so i am trying to multiplex the LVDS into 2 HSMC port. But i am not sure if this will work.

Any advice?

Regards,

Michael

You will need to perform your own register-to-register tests to determine what the maximum operating frequency is.

Processing frequencies of >150MHz should be possible.

Ultimately it will also depend on how much power you can afford to dissipate.

What speed LVDS did you need?

This board uses 125MHz LVDS on the front-panel connectors and 500MHz LVDS to interface to the 1GHz digitizers.

http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)

http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)

The digitizers test document has a discussion on the LVDS transceivers, along with scope captures, see p58 and on.

Cheers,

Dave