What is the processing speed limitation of Cyclone IV E with speed grade C7?

Hi Dave,

Yes, the speed grade for DE2-115 is C7, hence the LVDS receiver only goes up to 740MHz. (Table 1–36 (p466) of the latest Cyclone IV handbook), am i right?

I will first run the part with a lower frequency during the test. I know having a higher speed grade FPGA will probably fix all these speed issues, but i've already purchased the tPad(LCD + DE2-115)(costed me USD 850.00) for my senior design using my own money, so switching FPGA is probably not an option for me.

So back to my previous question. If i use 2 HSMC ports(all together 4 I/O) to receive the same LVDS signal, and my shift registers(14bits + 14bits) defined in verilog are running at half the speed of the LVDS signal. One group (14 bits) shift registers are triggered on the rising edge, while the other group (14 bits) shift registers are triggered on the falling edge.

In another words, i want the 2 HSMC ports to catch the LVDS data stream in alternate turns, to overcome the speed limitation issues. Do you think this approach will work? if no, what do you think is the limiting factor?

Thanks professor!

Regards,

Michael