What is the processing speed limitation of Cyclone IV E with speed grade C7?

Hi Michael,

Yes, the LVDS receiver is rated to 740Mbps (note: Mbps, not MHz).

So assuming you run the LVDS receiver in x7 mode, the data will enter the FPGA at ~105MHz. The ADC could be run at ~52MHz.

Unfortunately the scheme of using two LVDS receivers out-of-phase will not work. The issue will be that you cannot improve the setup/hold time of the receivers.

Adding an external clocked multiplexer would be a lot more trouble that its worth. I'd recommend starting out with the AFE operated at say 50MHz.

Would that be ok for your project?

Once you get the part operating at 50MHz, there is nothing to stop you from 'overclocking' your FPGA. You might be lucky and find that your board works fine at 910Mbps.

Cheers,

Dave