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Altera_Forum
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14 years ago

What is the processing speed limitation of Cyclone IV E with speed grade C7?

Hi everyone, Does anyone know, what is the maximum processing speed of Cyclone IV E (with speed grade of C7) within the FPGA fabric? Knowing that PLL on Cyclone IV E can generate up to 1....
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Altera_Forum
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14 years ago

You will need to perform your own register-to-register tests to determine what the maximum operating frequency is.

Processing frequencies of >150MHz should be possible.

Ultimately it will also depend on how much power you can afford to dissipate.

What speed LVDS did you need?

This board uses 125MHz LVDS on the front-panel connectors and 500MHz LVDS to interface to the 1GHz digitizers.

http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)

http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)

The digitizers test document has a discussion on the LVDS transceivers, along with scope captures, see p58 and on.

Cheers,

Dave