Honored Contributorhi ,everyone ,i have a question about the mulitplier.
i am a newer in FPGA ,now , i wonder the different between the mulitplier constusted by * in HDL and the one generated by Ip core ,what is the most important different between these two kinds of multipliers? the speed or any others? thaks
Honored ContributorI assume by IP core you mean "lpm_mult"?
Using lpm_mult you have more control over the multiplier unit to be target. Typing '*' into your code you are at the mercy of what the synthesis engine picks for you. So for portable coding '*' is a better approach but when you are tuning your design for performance or area you might need to resort to using lpm_mult. I recommend using '*' and when that doesn't give you the results you are looking for then try replacing it with an instantiation of lpm_mult.Honored Contributorthanks ,for your suggestion.
you mean that i can use the * for the primary design ,and if the synthesis result can't fit the target ,then i can usethe LPm_MULT instead for the second design to improve the function?Honored ContributorAn example of switching to lpm_mult would be if you determine features of the DSP/embedded multiplier block are not being utilized when the multiplier is inferred when you were counting on it. Sometimes it is not possible for the synthesis engine to map all the features of the hardware multipliers so using lpm_mult gives you the ability to do this.
In the Quartus II handbook there is a chapter called something like "HDL coding guidelines". It probably does a better job explaining this under the section about multiplication. I try to avoid using the LPMs whenever possible since I often create IP for different FPGA families and the hard block characteristics sometimes differ. So options of lpm_mult may vary between families which makes your implementation less portable as a result (you may not care about portability though).Honored ContributorThis post is timely, because I have been having an issue related to it. For larger multipliers, lpm_mult creates logic that is much faster. In my case of a signed 32x32 multiply, lpm_mult is double the speed of using "*" in Verilog. For a reference, here is my code:
module mult_test(
input CLK,
input signed IN_A,
input signed IN_B,
output signed OUT_C
);
//Verilog version
reg signed IN_A_d1;
reg signed IN_B_d1;
reg signed mult_result;
assign mult_result = IN_A_d1 * IN_B_d1;
always @(posedge CLK) begin
IN_A_d1 <= IN_A;
IN_B_d1 <= IN_B;
OUT_C <= mult_result;
end
/*
//Altera LPM Megafunction version
//Created as signed 32x32 -> 64-bit multiply with 2 cycles of latency
wire signed mult_result;
assign OUT_C = mult_result;
megafunction_mult megafunction_mult_inst (
.clock (CLK),
.dataa (IN_A),
.datab (IN_B),
.result (mult_result)
);*/
endmodule
I think it is to do with pipeline. You cannot pipeline internally with the inferred case as you did with lpm assuming a dedicated mult was generated in either case.
Honored ContributorI should mention that I copied the code format from "Example 10–2. Verilog HDL Signed Multiplier with Input and Output Registers (Pipelining = 2)" in the Quartus II handbook.
Honored ContributorTo improve speed further, you better register io of mult block and also insert registers between the block and fabric.
Honored Contributorcode portability of slow problematic design is never a good idea and defeats its purpose... common sense ??
Honored ContributorTry writing it the same way as shown in the multiplier template under the Edit menu. You can find it here under the templates: Verilog HDL --> Full Designs --> Arithmetic --> Multipliers --> Signed Multiply with Input and Output Registers.
Honored Contributor
