what is the different between * and IP core multiplier

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Try writing it the same way as shown in the multiplier template under the Edit menu. You can find it here under the templates: Verilog HDL --> Full Designs --> Arithmetic --> Multipliers --> Signed Multiply with Input and Output Registers.

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I just tried that, and it gave me the same result as my own hand-written Verilog.

So, the current fmax summary:

lpm_mult with two cycle latency = 180 MHz

Verilog * operation with input and output registers = 90 MHz

Quartus II Verilog signed multiply with I/O registers template = 90 MHz

My .sdc file is setup to try for 200 MHz in every case.