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Altera_Forum
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14 years ago

what is the different between * and IP core multiplier

hi ,everyone ,i have a question about the mulitplier. i am a newer in FPGA ,now , i wonder the different between the mulitplier constusted by * in HDL and the one generated by Ip core ,what is...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I should mention that I copied the code format from "Example 10–2. Verilog HDL Signed Multiplier with Input and Output Registers (Pipelining = 2)" in the Quartus II handbook.