What is the difference..?

Hello , I am starter in VHDL .

Is there any difference between two sources below?

They are different i think.

first source uses vector signal in the entity body.

second source uses vector signal in the architecture body.

is ther any difference? for example concurrent process or sequential process and so on..

I want to know what is the difference.

thanks!

( the difference of contents between two sources is not important for me.

i just want to know the differences in vhdl grammar)

(1)

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY tank is

PORT(

tank : IN std_logic_vector(2 downto 0);

alarm : OUT std_logic);

END tank;

ARCHITECTURE arc of tank is

BEGIN

WITH tank SELECT

alarm <= '0' when "000",

'0' when "001",

'0' when "010",

'1' when "011",

'0' when "100",

'1' when "101",

'1' when "110",

'1' when "111",

'0' when others;

END arc;

(2)

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY vector is

PORT(

a,b,c : IN std_logic;

x : OUT std_logic);

END vector;

ARCHITECTURE arc of vector is

SIGNAL input : std_logic_vector(2 downto 0); BEGIN

input(2)<=a;

input(1)<=b;

input(0)<=c;

WITH input SELECT

x <= '1' WHEN "000",.

'0' when "001",

'1' when "010",

'0' when "011",

'1' when "100",

'1' when "101",

'1' when "110",

'0' when "111",

END arc;