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Altera_Forum
Honored Contributor
14 years agoWhat is the difference..?
Hello , I am starter in VHDL . Is there any difference between two sources below? They are different i think. first source uses vector signal in the entity body. second source us...
Altera_Forum
Honored Contributor
14 years agoBoth codes will produce the same result. The only difference is that (1) takes a 3-bit vector as input and (2) takes 3 separate bits as inputs and regroups them in a vector.