Forum Discussion
Altera_Forum
Honored Contributor
14 years agoWhat is the difference..?
Hello , I am starter in VHDL . Is there any difference between two sources below? They are different i think. first source uses vector signal in the entity body. second source us...
Altera_Forum
Honored Contributor
14 years agoIn addition to Daixiwen, in (2) :
you forgot the case 'others' in the with...select you forgot ";" to close the with...select there is a point which goes for a trip after the first case of the with...select In conclusion, you can compile (1) but not (2).