Forum Discussion
New ContributorWatchdog Disable new SOC EDS Flow
Hi,
We are upgrading our flow to the new Bootloader build instructions as given in in https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10
With the previous flow, it was possible to disable the watchdog timer by Unchecking the option spl.boot.WATCHDOG_ENABLE when running the BSP-editor.
How is this done now in the new flow? We are not able to disable the HW_WATCHDOG when configuring U-boot before running the final make.
Any assistance would be appreciated.
Thanks
Hi Robert,
You can disable the watchdog from uboot using the new flow, the details in the github
https://github.com/altera-opensource/u-boot-socfpga
follow the build u-boot step in building bootloader
- Watchdog:
CFG_SYS_WATCHDOG_FREQ
Some platforms automatically call WATCHDOG_RESET()
from the timer interrupt handler every
CFG_SYS_WATCHDOG_FREQ interrupts. If not set by the
board configuration file, a default of CONFIG_SYS_HZ/2
(i.e. 500) is used. Setting CFG_SYS_WATCHDOG_FREQ
to 0 disables calling WATCHDOG_RESET() from the timer
interrupt.
You can use this step to disable the watchdog
Thank you,
Aliff
8 Replies
mabdrahiContributor
Hi Robert,
May i know your preferred step on your project?
Is it old step or new step?
Thank you.
Aliff
RobertGreenHi Aliff,
This would be a completely new step.
Regards,
-Robert
- mabdrahi
Hi Robert,
What is the quartus version are using?
Thank you,
Aliff
- RobertGreen
We are currently using 22.1
Regards,
-Robert
- mabdrahi
Hi Robert,
You can disable the watchdog from uboot using the new flow, the details in the github
https://github.com/altera-opensource/u-boot-socfpga
follow the build u-boot step in building bootloader
- Watchdog:
CFG_SYS_WATCHDOG_FREQ
Some platforms automatically call WATCHDOG_RESET()
from the timer interrupt handler every
CFG_SYS_WATCHDOG_FREQ interrupts. If not set by the
board configuration file, a default of CONFIG_SYS_HZ/2
(i.e. 500) is used. Setting CFG_SYS_WATCHDOG_FREQ
to 0 disables calling WATCHDOG_RESET() from the timer
interrupt.
You can use this step to disable the watchdog
Thank you,
Aliff
- mabdrahi
Hi Robert,
Anymore help you needed base on the solution given?
Thank you,
Aliff
- RobertGreen
Hi Aliff,
We decided to write to the CPU Watchdog reset registers in uboot to solve our issue, compiling with the CFG_SYS_WATCHDOG_FREQ set to 0 did not work as expected.
We can close this thread. Thank you for the assistance.
Regards,
-Robert
- mabdrahi
Hi Robert,
Thanks for the update, , I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you,
Aliff
