Forum Discussion
Watchdog Disable new SOC EDS Flow
- 2 years ago
Hi Robert,
You can disable the watchdog from uboot using the new flow, the details in the github
https://github.com/altera-opensource/u-boot-socfpga
follow the build u-boot step in building bootloader
- Watchdog:
CFG_SYS_WATCHDOG_FREQ
Some platforms automatically call WATCHDOG_RESET()
from the timer interrupt handler every
CFG_SYS_WATCHDOG_FREQ interrupts. If not set by the
board configuration file, a default of CONFIG_SYS_HZ/2
(i.e. 500) is used. Setting CFG_SYS_WATCHDOG_FREQ
to 0 disables calling WATCHDOG_RESET() from the timer
interrupt.
You can use this step to disable the watchdog
Thank you,
Aliff
Hi Robert,
Anymore help you needed base on the solution given?
Thank you,
Aliff
- RobertGreen2 years ago
New Contributor
Hi Aliff,
We decided to write to the CPU Watchdog reset registers in uboot to solve our issue, compiling with the CFG_SYS_WATCHDOG_FREQ set to 0 did not work as expected.
We can close this thread. Thank you for the assistance.
Regards,
-Robert