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RobertGreen's avatar
RobertGreen
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Watchdog Disable new SOC EDS Flow

Hi, We are upgrading our flow to the new Bootloader build instructions as given in in https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10 With the previous flow...
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  • mabdrahi's avatar
    mabdrahi
    2 years ago

    Hi Robert,


    You can disable the watchdog from uboot using the new flow, the details in the github

    https://github.com/altera-opensource/u-boot-socfpga


    follow the build u-boot step in building bootloader


    - Watchdog:

        CFG_SYS_WATCHDOG_FREQ

        Some platforms automatically call WATCHDOG_RESET()

        from the timer interrupt handler every

        CFG_SYS_WATCHDOG_FREQ interrupts. If not set by the

        board configuration file, a default of CONFIG_SYS_HZ/2

        (i.e. 500) is used. Setting CFG_SYS_WATCHDOG_FREQ

        to 0 disables calling WATCHDOG_RESET() from the timer

        interrupt.


    You can use this step to disable the watchdog


    Thank you,

    Aliff


mabdrahi's avatar
mabdrahi
Icon for Contributor rankContributor
2 years ago

Hi Robert,


Thanks for the update, , I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you,

Aliff