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Altera_Forum
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12 years ago

VIP - Clocked Video Output - No Vsync Signal (Help Please)

Hi

I'm new to the Altera's Video/Image IP suite so I set up a simple system in Qsys, Quartus v13.1: Test Pattern Gen (TPG) -> Clocked Video Output (CVO). My goal was to display basic color bar pattern on a VGA monitor. I'm using the Cyclone V SoCKit dev board.

- TPG is set at 1024x768 (3 parallel colors @ 8bits each).

- CVO is set at same res with syncs on "separate wires" option enabled. The CVO signals are connected to dev board VGA DAC (H+Vsyncs directly routed from the FPGA pins to the VGA connector).

- A PLL is used to generate 65MHz which is fed into the CVO as pixel clock while 130MHz is used as main clock for both TPG and CVO.

The Hsync, R, G, B signals appear to be correct but the Vsync signal is flat (logic 0) always. I'm baffled as to why the Vsync signal is not toggling. Given I haven't enabled user control feature for the TPG and CVO, I assume I don't need to do any initialization for these blocks (as in setting registers via NIOS).

Any suggestion on how to fix the Vsync would be really appreciated... Thanks in advance!!!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Okay I've tracked down the root cause. There seems to be a bug in the Qsys tool. Even though I set the resolution to 1024x768 in Test Pattern Gen GUI, the resolution was set as 1024x480 in .qsys file. See the section below. After I manually updated the file in a text editor (i.e. changed TPG_MAX_HEIGHT from 480 to 768) and recompiled the project, my setup TPG->CVO works fine now.

    I’m not sure why Qsys doesn’t correctly generate the system file. We shouldn't have to manually alter the .qsys file. I sent an email to Altera FAE.

    From .qsys File:

    ============

    <module kind="alt_vip_tpg" version="13.1" enabled="1" name="vip_tpg_vga_out">

    <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />

    <parameter name="CHANNELS_IN_PAR" value="3" />

    <parameter name="CTRL_INTERFACE_DEPTH" value="10" />

    <parameter name="PARAMETERISATION"><![CDATA[<testPatternGeneratorParams><TPG_NAME>MyPatternGenerator</TPG_NAME><TPG_RUNTIME_CONTROL>0

    </TPG_RUNTIME_CONTROL><TPG_BPS>8</TPG_BPS><TPG_MAX_WIDTH>1024</TPG_MAX_WIDTH><tpg_max_height>480</tpg_max_height…</parameter>

    </module>
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi mbp2014, I'm newbie

    I am trying to display a pattern on VGA monitor(640x480 resolution).

    I set 50MHz clock to the main clk of Test Pattern and CVO, 25MHz clock to pixel clock. But It still didnt work.

    .clk_25_clk(clk_50), // clk_25.clk

    .reset_reset_n(KEY[0]), // reset.reset_n

    .vga_clocked_video_vid_clk(clk_25), // vga_clocked_video.vid_clk

    .vga_clocked_video_vid_data(rgb_data), // .vid_data

    .vga_clocked_video_underflow(), // .underflow

    .vga_clocked_video_vid_datavalid(vid_datavalid), // .vid_datavalid

    .vga_clocked_video_vid_v_sync(v_sync), // .vid_v_sync

    .vga_clocked_video_vid_h_sync(h_sync), // .vid_h_sync

    .vga_clocked_video_vid_f(), // .vid_f

    .vga_clocked_video_vid_h(), // .vid_h

    .vga_clocked_video_vid_v() // .vid_v

    );

    assign VGA_SYNC_n = 1'b1;

    assign VGA_R = rgb_data[23:16];

    assign VGA_G = rgb_data[15:8];

    assign VGA_B = rgb_data[7:0];

    assign VGA_BLANK_n = vid_datavalid;

    assign VGA_CLK = clk_25;

    assign VGA_HS = h_sync;

    assign VGA_VS = v_sync;

    Is there anything wrong with my assignment?