Video designed with openLDI_TX degraded after power cycle

Hi Mingyuexin,

Apologize for the delayed response.

Thank you for your reply.

Regarding timing constrain, you may refer to I/O constrain in the Timing Analyzer Cookbook.

This document contains a collection of design scenarios, timing constraint guidelines, and techniques that you can apply to help optimize timing performance of your FPGA device.

You may refer to below documents for more information:

1. Intel® Quartus® Prime Timing Analyzer Cookbook
2. OpenLDI Interface Blocks for Qsys
3. Timing Analyzer Resource Center

We also have a demo design for OpenLDI. Please do note that this design is for demonstration purpose so they might have no timing constrains for the I/O.

For custom design, you may need to add the IO timing constrains for the I/O pins.

- OpenLDI TX/RX Built-In Self Test (BIST) Design Example

Hope this answers your question.

Thank you.

Best Regards,

ZH_Intel