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Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Video designed with openLDI_TX degraded after power cycle

Hi, I'm working on a customer board where we use OpenLDI module I found here (https://community.intel.com/t5/FPGA-Wiki/IP-Component-OpenLDI-FPD-Link-Camera-Link-VIP-Component-for-Qsys/ta-p/735654) ...
Generic Io
ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Mingyuexin,


Thank you for reaching out.

Apologize for the delayed response as we encounter some technical difficulty.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZH_Intel



  • Mingyuexin's avatar
    Mingyuexin
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi,

    Thank you very much for the response.

    I found that resetting CVO and OpenLDI would remove the issue.

    So I'm afraid there is timing issue between OpenLDI and the receiver chip on the board.

    OpenLDI utilize altlvds_tx to convert parallel data to serial data. Since it's a hardcore ip (SERDES), so I did not set any output timing constraint for the pins. So if timing constraint on the output pins are necessary, how to set then? There is no timing data from the datasheet of the receiver chip on the board either.

    Thank you very much for your time!

    With best wishes

    Mingyuexin