video clock skew

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Hi all

I made a video elaboration system using VIPcore and quartus9.2 web edition.

When I compile my project, sometimes i get correct timing analisys, and sometimes i found a critical warning about a clock skew (for the pixel clock and pixel data).

How can I force quartus2 to route some signals to have the minimum routing and clock delay?

best regards

phate

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Hi,

a clock skew is only defined between clocks not between clock and data. Clock skew means that you have a different clock routing delay between e.g. two registers. Did you get any timing violation in the timing analysis report (e.g. Hold time ).

Kind regards

GPK

Thakts for the reply.

Yes, I got this kind of messages

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Not operational: Clock Skew > Data Delay Nios_proc:inst1|alt_vip_cti_0:the_alt_vip_cti_0|alt_vip_cti_0_GN:auto_inst|alt_vip_Vid2IS:my_alt_vip_cti|alt_vip_Vid2IS_resolution_detection:resolution_detection|next_active_line_count[4]

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etc.

THIS time, I have 21 failed paths. Sometimes I get this error, sometimes no, but is a "random" behavior. I don't know why, but I would like to set up quartus compiler to have the rigth timing and rigth paths inside the fpga.

Vip are made by altera, so i belive there are some setting i did non set correctly in quartus to have correct timing routing...

kind regards

phate.

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Thakts for the reply.

Yes, I got this kind of messages

etc.

THIS time, I have 21 failed paths. Sometimes I get this error, sometimes no, but is a "random" behavior. I don't know why, but I would like to set up quartus compiler to have the rigth timing and rigth paths inside the fpga.

Vip are made by altera, so i belive there are some setting i did non set correctly in quartus to have correct timing routing...

kind regards

phate.

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Hi,

you should check for one path, which clock drives the source and which clock drives the receiving register. Are they identical ?

Kind regards

GPK

in the timing report windows there is written

"from" "to"

TD_CLK27 TD_CLK27

I suppose is the same clock

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in the timing report windows there is written

"from" "to"

TD_CLK27 TD_CLK27

I suppose is the same clock

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Hi,

do use the classic timing analyzer ? If yes, please list a path and post the result expanded ( so that we can see all ) here. In case you use TimeQuest please post the result

window of "report path".

Kind regards

GPK