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Hi all
I made a video elaboration system using VIPcore and quartus9.2 web edition.
When I compile my project, sometimes i get correct timing analisys, and sometimes i found a critical warning about a clock skew (for the pixel clock and pixel data).
How can I force quartus2 to route some signals to have the minimum routing and clock delay?
best regards
phate
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Hi,
a clock skew is only defined between clocks not between clock and data. Clock skew means that you have a different clock routing delay between e.g. two registers. Did you get any timing violation in the timing analysis report (e.g. Hold time ).
Kind regards
GPK
Honored Contributor
