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Altera_Forum's avatar
Altera_Forum
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16 years ago

video clock skew

Hi all I made a video elaboration system using VIPcore and quartus9.2 web edition. When I compile my project, sometimes i get correct timing analisys, and sometimes i found a critical warning ab...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Thakts for the reply.

Yes, I got this kind of messages

etc.

THIS time, I have 21 failed paths. Sometimes I get this error, sometimes no, but is a "random" behavior. I don't know why, but I would like to set up quartus compiler to have the rigth timing and rigth paths inside the fpga.

Vip are made by altera, so i belive there are some setting i did non set correctly in quartus to have correct timing routing...

kind regards

phate.

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Hi,

you should check for one path, which clock drives the source and which clock drives the receiving register. Are they identical ?

Kind regards

GPK