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Altera_Forum's avatar
Altera_Forum
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15 years ago

video clock skew

Hi all I made a video elaboration system using VIPcore and quartus9.2 web edition. When I compile my project, sometimes i get correct timing analisys, and sometimes i found a critical warning ab...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thakts for the reply.

Yes, I got this kind of messages

--- Quote Start ---

Not operational: Clock Skew > Data Delay Nios_proc:inst1|alt_vip_cti_0:the_alt_vip_cti_0|alt_vip_cti_0_GN:auto_inst|alt_vip_Vid2IS:my_alt_vip_cti|alt_vip_Vid2IS_resolution_detection:resolution_detection|next_active_line_count[4]

--- Quote End ---

etc.

THIS time, I have 21 failed paths. Sometimes I get this error, sometimes no, but is a "random" behavior. I don't know why, but I would like to set up quartus compiler to have the rigth timing and rigth paths inside the fpga.

Vip are made by altera, so i belive there are some setting i did non set correctly in quartus to have correct timing routing...

kind regards

phate.