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Honored ContributorVHDL robot design not working
Hello everybody I'm new in VHDL and I'm doing a project with DE2 board
In the project I need to build a robot. My first step was to design a ASM and from that to take out the FSM which i did (hopefully I did it good enough) The second step is to check one of my ASM and I choose my engine control ASM I wrote a program in VHDL using quartus and burn it into my board Instead of using the motors from the beginnig the idea was to used the board's led using a PWM generator that will create a "running led" effect for a curtain direction and in change it in a push of a button but it didn't work. Can anybody tell me what I did wrong? I think it's in the pin assignment34 Replies
Altera_Forumwhat are the warnings?
- Altera_Forum
thanks I dont know why it didnt work before , I open the project again and run it and it work maybe I need to do start simulate for every change I make in the project.
any way know that I played with multisim and I know how to run it more or less , I can go back to quartus and burn the code to the DE2 board with the original timing of DC 1ms (1khz that way I could see the leds running) and duty_cycle = 50000 cycles and see the leds running with the push of the button right? well at first I found some mistakes in the pin assignment and the reset was on '1' so I had to do some combine switching to see the leds running. but I'm not really seeing them running there all on all the time (running too fast for me to see ) and I can't make a 1 second delay because quartus is giving me 6 warnings on this kind of change DC : time:=1 sec; clock_period: time:=20 ns way ? and what changes do i need to make in order to see the leds running thanks in advance - Altera_Forum
heres the code I used:
As for the image - use printscreen key and paste it into paint.library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --use std.textio.all; --use ieee.std_logic_textio.all; ------------------------------------------------------------------------------ entity tb_pwm is end entity tb_pwm; ------------------------------------------------------------------------------ architecture arc_tb_pwm of tb_pwm is signal Clk : std_logic := '0'; -- signal Rst : std_logic := '0'; -- signal Sw : std_logic_vector (2 downto 0):= "000"; -- signal Enable : std_logic := '0'; -- signal Pwm : std_logic; -- signal Led : std_logic_vector(7 downto 0); -- begin test : entity work.pwm generic map( DC => 100 ns, clock_period => 20 ns ) port map ( Clk => Clk, Rst => Rst, Enable => Enable, Sw => Sw, Pwm => Pwm, Led => Led ); Clk <= not Clk after 10 ns; process begin wait until rising_edge(Clk); Enable <= '1'; rst <= '1'; wait until rising_edge(clk); rst <= '0'; Sw(0) <= '1'; Sw(1) <= '0'; Sw(2) <= '0'; wait for 100 ns; wait until rising_edge(clk); Sw(0) <= '0'; Sw(1) <= '1'; Sw(2) <= '0'; wait for 100 ns; wait until rising_edge(clk); Sw(0) <= '0'; Sw(1) <= '0'; Sw(2) <= '1'; wait for 100 ns; wait until rising_edge(clk); Enable <= '0'; wait for 100 ns; wait until rising_edge(clk); Rst <='0'; wait for 100 ns; end process; end architecture arc_tb_pwm; - Altera_Forum
that's nice are you sure you used me code
because I see different waves acutely the same waves I saw before another thing who do you upload the wave image like that? I put it into word - Altera_Forum
add a reset at the beginning of the process, like this:
and you'll get waves like this:begin wait until rising_edge(Clk); Enable <= '1'; rst <= '1'; wait until rising_edge(clk); rst <= '0'; - Altera_Forum
hi,
I changed the sw time to 50 ns even though I dont think its the problme, because the simulation still needed to display the sw waves and I only see clk wave and the others are : pwm - 'u' rst- 'x' others - '0' but know the clock time << sw time , so that solve this issue. I notice that I didnt included the generic map in the tb before so I did it now from a VHDL examples folder and I hope I did it right. but still there no changes in the waves ... so what now?:confused:library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --use std.textio.all; --use ieee.std_logic_textio.all; ------------------------------------------------------------------------------ entity tb_pwm is end entity tb_pwm; ------------------------------------------------------------------------------ architecture arc_tb_pwm of tb_pwm is signal Clk : std_logic := '0'; -- signal Rst : std_logic := '0'; -- signal Sw : std_logic_vector (2 downto 0):= "000"; -- signal Enable : std_logic := '0'; -- signal Pwm : std_logic; -- signal Led : std_logic_vector(7 downto 0); -- begin test : entity work.pwm generic map( DC => 100 ns, clock_period => 20 ns ) a port map ( Clk => Clk, Rst => Rst, Enable => Enable, Sw => Sw, Pwm => Pwm, Led => Led ); Clk <= not Clk after 10 ns; process begin wait until rising_edge(Clk); Enable <= '1'; wait until rising_edge(clk); Sw(0) <= '1'; Sw(1) <= '0'; Sw(2) <= '0'; wait for 100 ns; wait until rising_edge(clk); Sw(0) <= '0'; Sw(1) <= '1'; Sw(2) <= '0'; wait for 100 ns; wait until rising_edge(clk); Sw(0) <= '0'; Sw(1) <= '0'; Sw(2) <= '1'; wait for 100 ns; wait until rising_edge(clk); Enable <= '0'; wait for 100 ns; wait until rising_edge(clk); Rst <='0'; wait for 100 ns; end process; end architecture arc_tb_pwm; - Altera_Forum
your sw settings arnt held for long enough.
- Altera_Forum
I changed it to dC : time:=100 ns
that means 5 cycles so it should work right? but still no waves - Altera_Forum
the duty cycle is 50000, so you need at least this many clock cycles before LED is valid. Your entire simulation runs for 1 us at 100MHz, so you get a grand total of 100 clocks.
Another problem - you dont assert reset so your counter will never count (because it's all 'U' when it does try and count). - Altera_Forum
Hii again
the code has changed (add generic and a constant) and I am using the modelsim now insted of the active hdl but I still don't see any waves in the simulation :mad:library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; Entity Pwm is generic ( DC : time:=1 ms; clock_period: time:=20 ns ); Port ( Rst : In std_logic; Clk : In std_logic; Sw : In std_logic_vector (2 downto 0); Enable : in std_logic; Led : buffer std_logic_vector (7 downto 0); Pwm : Out std_logic ); attribute altera_chip_pin_lc: string; attribute altera_chip_pin_lc of Clk : signal is "@N2"; attribute altera_chip_pin_lc of Rst : signal is "@G26"; attribute altera_chip_pin_lc of Led : signal is "@AE23, @AF23, @AB21, @AC22, @AD22, @AD23, @AD21, @AC21"; attribute altera_chip_pin_lc of Sw : signal is "@N25,@N26, @P25"; attribute altera_chip_pin_lc of Enable: signal is "@AE14"; end entity Pwm; Architecture arc_Pwm of Pwm is constant duty_cycle: integer:=DC/clock_period; signal Counter : std_logic_vector (16 downto 0); begin PwmReg: process (Clk,Rst,Sw) begin if (Rst='1') then Counter <= (others=>'0'); Pwm <='0'; Led <= (others=>'0'); elsif rising_edge(Clk) then if (Enable='1') then if (Counter = duty_cycle) then Counter <= (others => '0'); if (Sw(0) = '1') and (Sw(1) = '0') and (Sw(2) = '0') then led <= led + 1; elsif (Sw(0) = '0') and (Sw(1) = '1') and (Sw(2) = '0') then led <= led - 1; end if; else Counter <= Counter + 1; end if; end if; if (Counter < duty_cycle) then Pwm <= '1'; else Pwm <= '0'; end if; end if; end process PwmReg; end architecture arc_Pwm;
In the do file I wrote 1us and in the tb iwrote 0.025us in order to see it in the simulaton thanks in advancelibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --use std.textio.all; --use ieee.std_logic_textio.all; ------------------------------------------------------------------------------ entity tb_pwm is end entity tb_pwm; ------------------------------------------------------------------------------ architecture arc_tb_pwm of tb_pwm is signal Clk : std_logic := '0'; -- signal Rst : std_logic := '0'; -- signal Sw : std_logic_vector (2 downto 0):= "000"; -- signal Enable : std_logic := '0'; -- signal Pwm : std_logic; -- signal Led : std_logic_vector(7 downto 0); -- begin test : entity work.pwm port map ( Clk => Clk, Rst => Rst, Enable => Enable, Sw => Sw, Pwm => Pwm, Led => Led ); Clk <= not Clk after 10 ns; process begin wait until rising_edge(Clk); --wait on switch push; Enable <= '1'; -- l1 : loop wait until rising_edge(clk); --wait for 1 ns; Sw(0) <= '1'; Sw(1) <= '0'; Sw(2) <= '0'; wait for 0.025us; wait until rising_edge(clk); Sw(0) <= '0'; Sw(1) <= '1'; Sw(2) <= '0'; wait for 0.025us; wait until rising_edge(clk); Sw(0) <= '0'; Sw(1) <= '0'; Sw(2) <= '1'; wait for 0.025us; wait until rising_edge(clk); Enable <= '0'; wait for 0.025us; wait until rising_edge(clk); Rst <='0'; wait for 0.025us; end process; end architecture arc_tb_pwm;
